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this is information on a product in full production. february 2014 docid022745 rev 9 1/25 25 STBB2 800 ma 2.5 mhz, high efficiency dual mode buck-boost dc-dc converter datasheet - production data features ? operating input voltage range from 2.4 v to 5.5 v ? 2% output voltage tolerance over process and temperature variations ? bypass power save function ? selectable output voltage with dedicated vsel pin ? very fast line and load transients ? 2.5 mhz switching frequency ? power save mode (ps) at light load ? typical efficiency higher than 90% ? 50 a max. quiescent current ? flip chip 20 bumps 0.4 mm pitch 2.1 x 1.8 mm applications ? memory card supply ? cellular phones description the STBB2 is a fixed frequency, high efficiency, buck-boost dc-dc converter which provides output voltages from 1.2 v to 4.5 v starting from input voltage from 2.4 v to 5.5 v. the device can operate with input voltages higher than, equal to, or lower than the output voltage making the product suitable for single li-ion, multi-cell alkaline or nimh applications where the output voltage is within the battery voltage range. the low-r ds(on) n-channel and p-channel mosfet switches are integrated and help to achieve high efficiency. the mode pin allows the selection between auto mode and forced pwm mode, taking advantage from either lower power consumption or best dynamic performance. the bypass function allows the battery power saving. in this operating mode, the high-side switches are turned on so that the output voltage is equal to the input voltage; in this condition the current consumption is reduced to a maximum of 5 a. the device also includes soft-start control, thermal shutdown, and current limit. the STBB2 is packaged in flip chip 20 bumps with 0.4 mm pitch. flip chip 20 (2.1 x 1.8 mm) table 1. device summary order codes markings packaging output voltages STBB2jad-r bb2 tape and reel adjustable STBB2j29-r b229 tape and reel 2.9 v / 3.4 v STBB2j30-r b230 tape and reel 3.0 v / 3.3 v www.st.com
contents STBB2 2/25 docid022745 rev 9 contents 1 application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 3 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 4 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 5 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 6 typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 7 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.1 dual mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.2 enable pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 7.3 bypass operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.4 vsel pin operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 7.5 protection features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5.1 soft-start and short-circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5.2 undervoltage lockout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7.5.3 overtemperature protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.1 programming the output voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.2 inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 8.3 input and output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.4 layout guidelines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 8.5 product evaluation board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 8.6 thermal consideration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 9 package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 10 revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
docid022745 rev 9 3/25 STBB2 application schematic 1 application schematic figure 1. application schematic for fixed version figure 2. application schematic for adjustable version note: all the above components refer to a typical application. operation of the device is not limited to the choice of these external components. table 2. typical external components component manufacturer part number value size c1 murata grm188r60j106m 10 f 0603 tdk-epc c1608x5r0j106m c2 murata grm188r61c105k 1 f 0603 c3, c4 murata grm188r60j106m 10 f 0603 tdk-epc c1608x5r0j106m l (1) 1. inductor used for the maximum power capability. optimized choice can be made according to the application conditions (see section 8 ). murata lqh3npn1r0nm0 1.0 h 3 x 3 x 1.4 mm coilcraft lps3015-102ml 3.0 x 3.0 x 1.5 mm tdk-epc vls252010et1r0n 2.5 x 2 x 1 mm r1 depending on the output voltage, 0 for fixed output version r2 depending on the output voltage, not used for fixed output version fb vout sw2 sw1 vin vina l1 pgnd gnd bp en mode vsel vina1 vbat c3 c4 c1 c2 fb vout sw2 sw1 vin vina l1 pgnd gnd bp en vsel mode vina1 vbat c1 c2 r1 r2 c4 c3
block diagram STBB2 4/25 docid022745 rev 9 2 block diagram figure 3. block diagram adjustable figure 4. block diagram fixed shut down en - + vref and soft-start - + device control osc - + - + gate driver otp uvlo fb vsel mode vsel bp gnd burst control 1 vina1 vina ea bp sw1 sw2 dmd dmd logic control vin vout comp 1 osc osc + - vsum vsum comp 2 burst control 2 level shift am10455v1 am10456v1 shut down en - + vref and soft-start - + device control osc - + - + gate driver otp uvlo fb vsel mode vsel bp gnd burst control 1 vina1 vina ea bp sw1 sw2 dmd dmd logic control vin vout comp 1 osc osc burst control 2 + - vsum vsum comp 2 vsel bp level shift
docid022745 rev 9 5/25 STBB2 absolute maximum ratings 3 absolute maximum ratings note: absolute maximum ratings are those values beyond which damage to the device may occur. functional operation under these conditions is not implied. table 3. absolute maximum ratings symbol parameter value unit vin, vina, vina1 supply voltage -0.3 to 7.0 v sw1,sw2 switching nodes -0.3 to 7.0 v vout output voltage -0.3 to 7.0 v mode, en, bp, vsel logic pins -0.3 to 7.0 v fb feedback pin -0.3 to 6.0 v esd human body model 2000 v charged device model 500 t amb operating ambient temperature -40 to 85 c t j maximum operating junction temperature 150 c t stg storage temperature -65 to 150 c table 4. thermal data symbol parameter value unit r thja thermal resistance junction-ambient 80 (1) c/w 1. pcb condition: jedec standard 2s2p(4-layer).
pin configuration STBB2 6/25 docid022745 rev 9 4 pin configuration figure 5. pin connections (top view) a4 [en] b4 [bp] c4 [mode] d4 [vsel] a3 [vina] b3 [vina1] c3 [gnd] d3 [gnd] a2 [vin] b2 [sw1] c2 [pgnd] d2 [sw2] a1 [vin] b1 [sw1] c1 [pgnd] d1 [sw2] e4 [gnd] e3 [fb] e2 [vo] e1 [vo] a4 [en] b4 [bp] c4 [mode] d4 [vsel] a3 [vina] b3 [vina1] c3 [gnd] d3 [gnd] a2 [vin] b2 [sw1] c2 [pgnd] d2 [sw2] a1 [vin] b1 [sw1] c1 [pgnd] d1 [sw2] e4 [gnd] e3 [fb] e2 [vo] e1 [vo] a4 [en] b4 [bp] c4 [mode] d4 [vsel] a3 [vina] b3 [vina1] c3 [gnd] d3 [gnd] a2 [vin] b2 [sw1] c2 [pgnd] d2 [sw2] a1 [vin] b1 [sw1] c1 [pgnd] d1 [sw2] e4 [gnd] e3 [fb] e2 [vo] e1 [vo] top view bottom view table 5. pin description pin name pin n description vout e1, e2 output voltage. sw2 d1, d2 switch pin - internal switches c and d are connected to this pin. connect inductor between sw1 to sw2. pgnd c1, c2 power ground. sw1 b1, b2 switch pin - internal switches a and b are connected to this pin. connect inductor between sw1 and sw2. en a4 enable pin. connect this pin to gnd or a voltage lower than 0.4 v to shut down the ic. a voltage higher than 1.2 v is required to enable the ic. do not leave this pin floating. mode c4 when in normal operation, the mode pin selects between auto mode and forced pwm mode. if the mode pin is low, the STBB2 automatically switches between pulse-skipping and standard pwm according to the load level. if the mode pin is pulled high, the STBB2 always works in pwm mode. do not leave this pin floating. vina a3 supply voltage for control stage. vina1 b3 a 100 resistor is internally connected between vin and vina1. connecting a 1 f capacitor between vina1 and gnd. vin a1, a2 power input voltage. connect a ceramic bypass capacitor (10 f min.) between this pin and pgnd. gnd c3, d3, e4 signal ground. fb e3 feedback voltage. for the fixed version this pin must be connected to v out .
docid022745 rev 9 7/25 STBB2 pin configuration bp b4 bypass mode selection. when en is high, connecting this pin to a voltage higher than 1.2 v, the device works in bypass mode. a voltage lower than 0.4 v is required to disable bypass mode. in bypass mode vin is shorted to v out through internal switches. do not leave this pin floating. vsel d4 selection of output voltage for fixed versions (0 v out = 2.9 v / 1 v out = 3.4 v), (0 v out = 3.0 v / 1 v out = 3.3 v). this feature is not present in the adjustable version where the vsel pin must be connected to vina. do not leave this pin floating. table 5. pin description (continued) pin name pin n description
electrical characteristics STBB2 8/25 docid022745 rev 9 5 electrical characteristics - 40 c < t a < 85 c, v in = 3.6 v; v out = 3.4 v, v en = v in , v bp = 0 v; typical values are at t a = 25 c, unless otherwise specified. table 6. electrical characteristics symbol parameter test conditions min. typ. max. unit general section v in operating power input voltage range 2.4 5.5 v i q shutdown mode v en = 0 v 0.5 2 a pulse-skipping i out = 0 a, v mode = 0 35 50 a pwm mode i out = 0 a, v mode = v in 810ma bypass mode v bp = v in ; i out = 0 a; v mode = 0, v in = 2.4 to 5.5 v 510a v uvlo undervoltage lockout threshold v in rising; v mode = v in; i out = 100 ma 2.1 2.35 v v in falling; v mode = v in; i out = 100 ma 1.8 2.1 f sw switching frequency 2 2.5 3 mhz i out continuous output current (1) 2.5 v v in 5.5 v 800 ma i pk switch current limitation 2.4 2.5 2.7 a i ps-pwm ps to pwm transition 300 ma pwm to ps transition 280 h efficiency (v in = 3.6 v; v out = 3.4 v) i out =1 0 ma (ps mode) 85 % i out = 50 ma (ps mode) 90 i out = 150 ma (pwm) 90 i out = 250 ma (pwm) 91 i out = 500 ma (pwm) 92 i out = 800 ma (pwm) 92 t on turn-on time (2) v en from low to high; i out = 10 ma 260 300 s t shdn thermal shutdown 150 c hysteresis 20 c output voltage v out output voltage range 1.2 4.5 v
docid022745 rev 9 9/25 STBB2 electrical characteristics %v out output voltage accuracy in pwm mode v in = 2.5 to 5.5 v, v mode = v in v sel = gnd/v in -1.5 +1.5 % output voltage accuracy in power save mode v in = 2.5 to 5.5 v, v mode = gnd v sel = gnd/v in suitable output current to keep ps operation -3 +3 % v fb feedback voltage accuracy adjustable version 493 500 507 mv %v out maximum load regulation i load = from 10 ma to 800 ma 0.5 % v opp-ps peak-to-peak ripple in ps mode i out = 100 ma 130 mv i lkfb fb pin leakage current v fb = 5.5 v 9 a logic inputs v il low-level input voltage (en, mode, bp, vsel pins) 0.4 v v ih high-level input voltage (en, mode, bp, vsel pins) 1.2 v i lk-i input leakage current (en, mode, bp, vsel pins) v en =v mode =v bp =v sel = 5.5 v 0.01 1 a power switches r ds(on) p-channel on-resistance 130 350 m n-channel on-resistance 130 350 m i lkg-p p-channel leakage current v in = v out = 5.5 v; v en = 0 1 a i lkg-n n-channel leakage current v sw1 = v sw2 = 5.5 v; v en = 0 1 a 1. not tested in production. this value is guaranteed by correlation with r ds(on) , peak current limit and operating input voltage. 2. not tested in production. table 6. electrical characteristics (continued) symbol parameter test conditions min. typ. max. unit
typical performance characteristics STBB2 10/25 docid022745 rev 9 6 typical performance characteristics figure 6. maximum output current vs. input voltage table 7. table of graphs maximum output current vs. input voltage figure 5 efficiency vs. output current (power save enabled, v in = 2.5 v, 3.6 v, 4.5 v/v out = 3.4 v) figure 6 vs. output current (power save disabled, v out = 2.5 v, 3.6 v, 4.5 v/ v out = 3.4 v) figure 7 vs. output current (power save enabled, v in = 2.5 v, 3.6 v, 4.5 v/v out = 2.9 v) figure 8 vs. output current (power save disabled, v out = 2.5 v, 3.6 v, 4.5 v/ v out = 2.9 v) figure 9 vs. input voltage power save enabled, v out = 3.4 v, i out = (10; 50; 150; 500; 800 ma) figure 10 vs. input voltage power save disabled, v out = 3.4 v, i out = (10; 500; 1000; 2000 ma) figure 12 vs. output current (pwm/auto mode) figure 13 waveforms load transient response v in < v out figure 14 load transient response v in > v out figure 15 line transient response (v out = 3.3 v, i out = 1500 ma) figure 16 startup after enable (v out = 3.3 v, v in = 2.4 v, i out = 300 ma) figure 17 startup after enable (v out = 3.3 v, v in = 4.2 v, i out = 300 ma) figure 18 am10444v1 0 200 400 600 800 1000 1200 1400 1600 1800 2000 2200 2 2.5 3 3.5 4 4.5 5 5.5 i out max [ ma] v in [v] v out = 2.9 v v out = 3.4 v
docid022745 rev 9 11/25 STBB2 typical performance characteristics figure 7. efficiency vs. output current (power save mode enabled v out = 3.4 v) figure 8. efficiency vs. output current (power save mode disabled v out = 3.4 v) figure 9. efficiency vs. output current (power save mode enabled v out = 2.9 v) 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 eff [%] i out [ma] = vin v 2.5 = vin v 3.6 = vin v 4.5 enabled power save mode v out = 3.4 v am01436v1 am10437v1 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 eff [%] i out [ma] vin = 2.5v vin = 3.6v vin = 4.5v v out = 3.4 v power save mode disabled am10438v1 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 eff [%] i out [ma] vin = 2.5v vin = 3.6v vin = 4.5v v out = 2.9 v power save mode enabled
typical performance characteristics STBB2 12/25 docid022745 rev 9 figure 10. efficiency vs. output current (power save mode disabled v out = 2.9 v) figure 11. efficiency vs. input voltage (power save enabled, v out = 3.4 v) figure 12. efficiency vs. input voltage (power save disabled, v out = 3.4 v) am10439v1 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 eff [%] i out [ma] vin=2.5v vin=3.6v vin=4.5v v out = 2.9 v power save mode disabled am10440v1 0 10 20 30 40 50 60 70 80 90 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 eff [%] v in [v] iout = 10 ma iout = 50 ma iout = 150 ma iout = 500 ma iout = 800 ma power save mode v out = 3.4 v am10441v1 0 10 20 30 40 50 60 70 80 90 100 2.5 3.0 3.5 4.0 4.5 5.0 5.5 eff [%] v in [v] iout=10 ma iout=50 ma iout =150 ma iout=500 ma iout=800 ma power save mode v out = 3.4 v
docid022745 rev 9 13/25 STBB2 typical performance characteristics figure 13. efficiency vs. output current (pwm / auto mode) figure 14. v in = 2.4 v, v out = 3.4 v, i out = from 80 ma to 630 ma figure 15. v in = 4.2 v, v out = 3.4 v, i out = from 80 ma to 1100 ma am10442v1 0 10 20 30 40 50 60 70 80 90 100 1 10 100 1000 eff [%] i out [ma] vin=2.5v pwm mode vin=2.5v auto mode v out = 3.4 v time base 1 msec output voltage 200 mv/div , ac output current 500 ma/div v out = 3.4 v input voltage 200 mv/div, dc offset 2.46 output current 500 ma/div output voltage 200 mv/div, ac v out = 3.4 v time base 1 msec input voltage 200 mv/div, dc offset 4.2 v
typical performance characteristics STBB2 14/25 docid022745 rev 9 figure 16. v in = from 3.6 v to 4 v, v out = 3.4 v, i out = 300 ma figure 17. startup after enable (v out = 3.3 v, v in = 2.4 v, i out = 300 ma) figure 18. startup after enable (v out = 3.3 v, v in = 4.2 v, i out = 300 ma) input voltage 400 mv/div, offset = 3.6 v output voltage 20 mv/div timebase 1 msec sw2 sw1 v out i sw sw2 sw1 v out i sw
docid022745 rev 9 15/25 STBB2 general description 7 general description the STBB2 is a high efficiency dual mode buck-boost switch mode converter. thanks to the 4 internal switches, 2 p-channels and 2 n-channels, it is able to deliver a well-regulated output voltage using a variable input voltage which can be higher than, equal to, or lower than the desired output voltage. this solves most of the power supply problems that circuit designers face when dealing with battery powered equipment. the controller uses an average current mode technique in order to obtain good stability in all possible conditions of input voltage, output voltage and output current. in addition, the peak inductor current is monitored to avoid saturation of the coil. the STBB2 can work in two different modes: pwm mode or power save mode. in the first case, the device operates with a fixed oscillator frequency in all line/load conditions. this is the suitable condition to obtain the maximum dynamic performance. in the second case the device operates in burst mode allowing a drastic reduction of the power consumption. top-class line and load transients are achieved thanks to a feed-forward technique and due to the innovative control method specifically designed to optimize the performance in the buck-boost region where input voltage is very close to the output voltage. the STBB2 is self-protected from short-circuit and overtemperature. undervoltage lockout and soft-start guarantee proper operation during startup. input voltage and ground connections are split into power and signal pins. this allows reduction of internal disturbances when the 4 internal switches are working. the switch bridge is connected between the v in and pgnd pins while all logic blocks are connected between v ina and gnd. 7.1 dual mode operation the STBB2 works at fixed frequency pulse width modulation (pwm) or in power save mode (ps) according to the different operating conditions. if the mode pin is pulled high the device works at fixed frequency pulse width modulation (pwm) even at light or no load. in this condition, the STBB2 provides the best dynamic performance. if the mode pin is logic low, the STBB2 operation changes according to the average input current handled by the device. at low average current the STBB2 is in ps mode allowing very low power consumption and therefore obtaining very good efficiency event at light load. when the average current increases, the device automatically switches to fixed switching frequency mode in order to deliver the power needed by the load. in ps mode the STBB2 implements a burst mode operation: if the output voltage increases above its nominal value the device stops switching; as soon the v out falls below the nominal value the device restarts switching. 7.2 enable pin the device turns on when the en pin is pulled high. if the en pin is low the device goes to shutdown mode and all internal blocks are turned off. in shutdown mode the load is electrically disconnected from the input to avoid unwanted current leakage from the input to the load and the current drawn from the battery is lower than 1 a in the whole temperature range.
general description STBB2 16/25 docid022745 rev 9 7.3 bypass operation in bypass mode the output is connected directly to the battery by two p-channels and the inductor. the bypass function has been implemented in order to save energy when the application is in idle mode. at light load condition, the device can be in bypass mode to reduce the current drained from the battery. in bypass mode the quiescent current is around 5 a. without bypass function, the buck-boost works in pulse-skipping mode with around 50 a of current consumption. the device can be placed in bypass mode by the byp pin. 7.4 vsel pin operation for the fixed output voltage version, the fb pin must be connected to the v out pin. fixed output voltage versions have two different output voltages programmed internally which are selected by programming high or low at vsel. the higher output voltage is selected by programming vsel high and the lower output voltage is selected by programming vsel low. this feature is not present in the adjustable version, where the vsel pin must be connected to v ina . table 8. bypass and enable matrix en bp mode status 00 0 shutdown 00 1 shutdown 01 0 shutdown 01 1 shutdown 1 0 0 auto mode 10 1 pwm mode 1 1 0 bypass 1 1 1 bypass table 9. output selection p/n v sel v out STBB2j-29 low 2.9 v high 3.4 v STBB2j-30 low 3.0 v high 3.3 v
docid022745 rev 9 17/25 STBB2 general description 7.5 protection features 7.5.1 soft-start and short-circuit after the en pin is pulled high, the device initiates the start-up phase. the average current limit is set to 400 ma at the beginning and is gradually increased while the output voltage increases. as soon as the output voltage reaches 1.0 v, the average current limit is set to its nominal value. this method allows a current limit proportional to the output voltage. if there is a short in the v out pin, the output current does not exceed 400 ma. this process is not handled by a timer so the device is also able to start up even with large capacitive loads. 7.5.2 undervoltage lockout the undervoltage lockout function prevents improper operation of the STBB2 when the input voltage is not high enough. when the input voltage is below the vuvlo threshold, the device is in shutdown mode. the hysteresis of 100 mv prevents unstable operation when the input voltage is close to the uvlo threshold. 7.5.3 overtemperature protection an internal temperature sensor continuously monitors the ic junction temperature. if the ic temperature exceeds 150 c (typ.), the device stops operating. as soon as the temperature falls below 130 c (typ.), normal operation is restored.
application information STBB2 18/25 docid022745 rev 9 8 application information 8.1 programming the output voltage the STBB2 is available in two versions: fixed output voltage and adjustable output voltage. in the first case the device integrates the resistor divider needed to set the correct output voltage and the fb pin must be connected directly to v out . for the fixed version, two different output voltages, programmed internally by the vsel pin, can be selected. for the adjustable version, the vsel pin must be connected to v in . the resistor divider must be connected between v out and gnd and the middle point of the divider must be connected to fb as shown in figure 19 . equation 1 figure 19. adjustable output voltage a suggested value for r2 is 100 k . to reduce the power consumption a maximum value of 500 k can be used. 8.2 inductor selection the inductor is the key passive component for switching converters. with a buck-boost device, the inductor selection must take into consideration the following two conditions in which the converter works: ? as buck at the maximum operative input voltage of the application ? as a boost at the minimum operative input voltage of the application two critical inductance values are then obtained according to the following formulas: ? ? ? ? ? ? ? ? ? = 1 v v 2 r 1 r fb out am10443v1 l1 c4 r1 c1 r2 c2 c3 gnd gnd gnd gnd fb e3 gnd c3 gnd d3 pgnd c2 mode c4 vsel d4 bp b4 en a4 vina a3 vin a1 vout e2 pgnd c1 vout e1 gnd e4 sw2 d2 sw2 d1 sw1 b1 sw1 b2 vin a2 vina1 b3 STBB2 gnd gnd gnd gnd
docid022745 rev 9 19/25 STBB2 application information equation 2 equation 3 where fs is the minimum value of the switching frequency and i l is the peak-to-peak inductor ripple current. the peak-to-peak ripple can be set at 10% or 20% of the output current. the minimum inductor value for the application is the highest between equation 2 and equation 3 . in addition to the inductance value, the maximum current, which the inductor can handle, must be calculated in order to avoid saturation. equation 4 equation 5 where is the estimated efficiency. the maximum of the two above values must be considered when the inductor is selected. 8.3 input and output capacitor selection it is recommended ceramic capacitors to be used with low esr as input and output capacitors in order to filter any disturbance present in the input line and to obtain stable operation. minimum values of 10 f for both capacitors are needed to achieve good behavior of the device. the input capacitor must be placed as closer as possible to the device. 8.4 layout guidelines due to the high switching frequency and peak current, the layout is an important design step for all switching power supplies. if the layout is not fulfilled carefully, important parameters such as efficiency and output voltage ripple may be compromised. l max max buck min i fs vin ) vout vin ( vout l ? = ? ? = ? ? + = ? ? + = ?
application information STBB2 20/25 docid022745 rev 9 short and wide traces must be implemented for main current and for power ground paths. the input capacitor must be placed as closer as possible to the device pins as well as the inductor and output capacitor. the feedback pin (fb) is a high impedance node, so the interference can be minimized by placing the routing of the feedback node as far as possible from the high current paths. a common ground node minimizes ground noise. 8.5 product evaluation board figure 20. assembly layer figure 21. top layer
docid022745 rev 9 21/25 STBB2 application information figure 22. bottom layer 8.6 thermal consideration to enhance the thermal performance, the power dissipation capability of the pcb design can be improved by traces as wider as possible. the maximum recommended junction temperature (t j ) of the devices is 125 c. the junction ambient thermal resistance of this 20-pin flip chip package is 80 c/w, if all pins are soldered. to the maximum ambient temperature t a = 85 c the maximum power dissipated inside the package is given by: equation 6 p diss_max = (t jmax - t amax ) / r ja = (125 - 85) / 80 = 500 mw
package mechanical data STBB2 22/25 docid022745 rev 9 9 package mechanical data in order to meet environmental requirements, st offers these devices in different grades of ecopack ? packages, depending on their level of environmental compliance. ecopack specifications, grade definitions and product status are available at: www.st.com. ecopack is an st trademark. figure 23. flip chip 20 (2.1 x 1.8 mm) package dimensions 7504889_g
docid022745 rev 9 23/25 STBB2 package mechanical data table 10. flip chip 20 (2.1 x 1.8 mm) mechanical data dim. mm min. typ. max. a 0.52 0.56 0.60 a1 0.17 0.23 a2 0.35 0.36 0.37 b 0.23 0.25 0.29 d 2.03 2.06 2.09 d1 1.6 e 1.71 1.74 1.77 e1 1.2 e0.40 se 0.20 fd 0.23 fe 0.27 ccc 0.075
revision history STBB2 24/25 docid022745 rev 9 10 revision history table 11. document revision history date revision changes 27-jan-2012 1 first release. 27-mar-2012 2 datasheet promoted from preliminary data to production data. removed: order code STBB2j28-r table 1 on page 1 . 09-may-2012 3 modified: marking bb2 table 1 on page 1 , description pin b4 and d4 table 5 on page 6 . 26-jul-2012 4 modified: c2 value table 2 on page 3 . updated: figure 20 , figure 21 and figure 22 on page 21 . 19-sep-2012 5 modified: figure 2 on page 3 . 06-mar-2013 6 added: new order code STBB2j33-r table 1 on page 1 . 17-dec-2013 7 changed order code from the STBB2j33-r to the STBB2j30-r in table 1: device summary and in table 9: output selection . changed v opp-ps typ. value from 100 to 130 in table 6: electrical characteristics . minor text changes. 20-jan-2014 8 updated mechanical data. 12-feb-2014 9 updated features and description in cover page. changed typ. and max. values of v uvlo parameter in table 6 . changed v in min. value in table 6 . changed v in test conditions of i q parameter in table 6 . changed i pk min. value in table 6 . updated table 7 .
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